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AMD Mobile Serial VID Dual-Phase
Fixed-Frequency Controller
Pin Description
PIN
1
NAME
PWRGD
FUNCTION
Open-Drain, Power-Good Output. PWRGD indicates when both SMPSs are in regulation.
PWRGD is forced high impedance whenever the slew-rate controller is active (output-voltage
transitions). After output-voltage transitions, except during power-up and power-down, if FBDC_ is in
regulation, then PWRGD is high impedance.
During startup, PWRGD is held low an additional 20 μs after the MAX17009 reaches the startup boot
voltage set by the SVC, SVD pins. The MAX17009 stores the boot VID when PWRGD first goes high.
The stored boot VID is cleared by rising SHDN .
PWRGD is forced low in shutdown.
When in pulse-skipping mode, the upper PWRGD threshold comparator is blanked during a lower VID
transition. The upper PWRGD threshold comparator is reenabled once the output is in regulation (Figure 4).
North Bridge Buffered Reference Voltage. This output is connected to the REFIN input of the NB
controller (switcher or LDO) to set the NB regulator voltage. The NBV_BUF output current is set by the
TIME resistor. The NBV_BUF current and the total output capacitance set the NBV_BUF slew rate:
2
NBV_BUF
I NBV_BUF = (7μA) x (143k
/ R TIME )
NBV_BUF Slew rate = I NBV_BUF / C NBV_BUF
I NBV_BUF is the same during startup, shutdown, and any VID transition.
Bypass to GND with a 100pF minimum low-ESR (ceramic) capacitor at the NBV_BUF pin.
Shutdown Control Input. Connect high (2V to V CC ) for normal operation. Connect to ground to put the IC
into its 1μA max shutdown state.
During startup, the SMPS output voltages and the NBV_BUF voltage are ramped up to the voltage set
by the SVC, SVD inputs. The SMPSs start up and shut down at a fixed slew rate of 1mV/μs.
3
SHDN
SVC
0
0
1
1
SVD
0
1
0
1
BOOT VOLTAGE (V BOOT )
( PRO = V CC OR GND)
1.1
1.0
0.9
0.8
BOOT VOLTAGE (V BOOT )
( PRO = OPEN)
1.1
1.2
1.0
0.8
The MAX17009 stores the boot VID when PWRGD first goes high. The stored boot VID is cleared by
rising SHDN .
2.0V Reference Output. Bypass to GND with a 1 μF maximum low-ESR (ceramic) capacitor. REF
4
5
REF
ILIM
sources up to 500μA for external loads. Loading REF degrades output accuracy, according to the REF
load-regulation error.
Current-Limit Adjust Input. The positive current-limit threshold voltage is precisely 1/20 of the voltage
between REF and ILIM over a 0.2V to 1.0V range of V(REF, ILIM). The I MIN minimum current-limit threshold
voltage in skip mode is precisely 15% of the corresponding positive current-limit threshold voltage.
Oscillator Adjustment Input. Connect a resistor (R OSC ) between OSC and GND to set the switching
frequency (per phase):
6
OSC
f OSC = 300kHz x 143k
/ R OSC
A 35.7k
to 432k
corresponds to switching frequencies of 1.2MHz to 100kHz, respectively.
Switching-frequency selection is limited by the minimum on-time. See the Switching frequency bullet
in the SMPS Design Procedure section.
______________________________________________________________________________________
15
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